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| FIN24AC 22-Bit Bi-Directional Serializer/Deserializer January 2007 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Features Low power for minimum impact on battery life tm General Description The FIN24AC SerDesTM is a low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. For bi-directional operation, using half duplex for multiple sources, it is possible to increase the signal reduction to close to 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. The differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. A unique word boundary technique assures that the actual word boundary is identified when the data is deserialized. This guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. A single PLL is adequate for most applications, including bi-directional operation. - Multiple power-down modes - AC coupling with DC balance 100nA in standby mode, 5mA typical operating conditions Cable reduction: 25:4 or greater Bi-directional operation 50:7 reduction or greater Differential signaling: - -90dBm EMI when using CTL in lab conditions using a near field probe - Minimized shielding - Minimized EMI filter - Minimum susceptibility to external interference Up to 22 bits in either direction Up to 20MHz parallel interface operation Voltage translation from 1.65V to 3.6V Ultra-small and cost-effective packaging High ESD protection: >8kV HBM Parallel I/O power supply (VDDP) range between 1.65V to 3.6V Applications Micro-controller or pixel interfaces Image sensors Small displays - LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive Ordering Information Order Number FIN24ACGFX FIN24ACMLX Package Number BGA042 MLP040 Pb-Free Yes Yes Package Description 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. SerDesTM is a trademark of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Functional Block Diagram CKREF STROBE Register PLL 0 cksint I Word Boundary Generator + - CKS0+ CKS0- DP[21:22] Serializer Control Serializer + - DSO+/DSIDSO-/DSI+ DP[1:20] oe Register Register Deserializer Deserializer Control cksint + - + - 100 Gated Termination CKSI+ CKSI100 Termination DP[23:24] CKP WORD CK Generator Control Logic S1 S2 DIRI Power Down Control Freq. Control Direction Control oe DIRO Figure 1. Block Diagram (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 2 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Terminal Description Terminal Name DP[1:20] DP[21:22] DP[23:24] CKREF STROBE CKP DSO+ / DSI- DSO- / DSI+ I/O Type I/O I O IN IN OUT DIFF-I/O Number of Terminals 20 2 2 1 1 1 2 Description of Signals LVCMOS Parallel I/O, direction controlled by DIRI pin LVCMOS Parallel Unidirectional Inputs LVCMOS Unidirectional Parallel Outputs LVCMOS Clock Input and PLL Reference LVCMOS Strobe Signal for Latching Data into the Serializer LVCMOS Word Clock Output CTL Differential Serial I/O Data Signals(1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)-: Negative signal of DSO(I) pair CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI-: Negative signal of CKSI pair CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO-: Negative signal of CKSO pair LVCMOS Mode Selection terminals used to select Frequency Range for the RefClock, CKREF LVCMOS Control Input Used to control direction of Data Flow: DIRI = "1" Serializer, DIRI = "0" Deserializer LVCMOS Control Output Inversion of DIRI Power Supply for Parallel I/O and Translation Circuitry Power Supply for Core and Serial I/O Power Supply for Analog PLL Circuitry Use Bottom Ground Plane for Ground Signals CKSI+, CKSI- DIFF-IN 2 CKSO+, CKSO- DIFF-OUT 2 S1 S2 DIRI IN IN IN 1 1 1 DIRO VDDP VDDS VDDA GND OUT Supply Supply Supply Supply 1 1 1 1 0 Note: 1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180 to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 3 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Connection Diagrams 32 STROBE 19 DP[9] DP[10] DP[11] DP[12] VDDP CKP DP[13] DP[14] DP[15] DP[16] 31 CKREF 30 DIRO 29 CKSO+ 28 CDSO27 DSO+ / DSI26 DSO- / DSI+ 25 CKSI24 CKSI+ 23 DIRI 22 S2 21 VDDS 40 DP[8] 39 DP[7] 38 DP[6] 37 DP[5] 36 DP[4] 35 DP[3] 16 34 DP[2] 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 33 DP[1] Figure 2. Terminal Assignments for MLP (Top View) 1 A B C D E F J 2 3 4 5 6 DP[17] DP[18] DP[19] DP[20] DP[21] DP[22] DP[23] DP[24] S1 VDDA Pin Assignments 1 A B C D E F J DP[9] DP[11] CKP DP[13] DP[15] DP[17] DP[19] 2 DP[7] DP[10] DP[12] DP[14] DP[16] DP[18] DP[20] 3 DP[5] DP[6] DP[8] VDDP GND DP[21] DP[22] 4 DP[3] DP[2] DP[4] GND VDDS VDDA DP[23] 5 DP[1] STROBE CKSO+ CKSI+ S2 DP[24] 6 CKREF DIRO CKSOCKSIDIRI S1 20 DSO- / DSI+ DSO+ / DSI- (Top View) Figure 3. Terminal Assignments for BGA (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 4 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Control Logic Circuitry The FIN24AC has the ability to be used as a 24-bit Serializer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the pin programming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device is configured as a serializer. Changing the state on the DIRI signal reverses the direction of the I/O signals and generates the opposite state signal on DIRO. For unidirectional operation, the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bidirectional operation, the DIRI of the master device is driven by the system and the DIRO signal of the master is used to drive the DIRI of the slave device. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken during design to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be in a HIGH-impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten. Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, LVCMOS inputs are driven to a valid level internally, and all internal circuitry is reset. The loss of CKREF state is also enabled to ensure that the PLL only powers up if there is a valid CKREF signal. In a typical application, signals do not change states other than between the desired frequency range and the powerdown mode. This allows for system-level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a "logic 0" should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a "logic 1" should be connected to a system level power-down signal. Serializer/Deserializer with Dedicated I/O Variation The serialization and deserialization circuitry is setup for 24 bits. Because of the dedicated inputs and outputs, only 22 bits of data are ever serialized or deserialized. Regardless of the mode of operation, the serializer is always sending 24 bits of data and two boundary bits and the deserializer is always receiving 24 bits of data and two word boundary bits. Bits 23 and 24 of the serializer always contain the value of zero and are discarded by the deserializer. DP[21:22] input to the serializer is deserialized to DP[23:24] respectively. Table 1. Control Logic Circuitry Mode Number 0 1 2 3 S2 0 0 0 1 1 1 1 S1 0 1 1 0 0 1 1 DIRI x 1 0 1 0 1 0 Power-Down Mode Description 24-Bit Serializer, 2MHz to 5MHz CKREF 24-Bit Deserializer 24-Bit Serializer, 5MHz to 15MHz CKREF 24-Bit Deserializer 24-Bit Serializer, 10MHz to 20MHz CKREF 24-Bit Deserializer (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 5 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works essentially the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the STROBE signal or not. When the CKREF equals STROBE, the CKREF and STROBE signals have an identical frequency of operation, but may or may not be phase aligned. When CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure 4) MODE 1, 2, or 3 DIRI = 1, CKREF = STROBE The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When in this mode, the internal deserializer circuitry is disabled; including the serial clock, serial data input buffers, the bi-directional parallel outputs, and the CKP word clock. The CKP word clock is driven HIGH. WORD n WORD n+1 DPI[1:24] CKREF DSO CKS0 WORD n-1 b24 b25 b26 b1 b2 b3 b4 b22 b23 b24 b25 b26 b1 b2 b3 b4 b5 WORD n-2 WORD n-1 WORD n Figure 4. Serializer Timing Diagram (CKREF equals STROBE) Serializer Operation: (Figure 5), DIRI = 1, CKREF does not = STROBE If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 26 times the CKREF frequency. A data bit value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs is dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology, the maximum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-tocycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. CKREF DP[1:24] STROBE DSO CKS0 No Data WORD n-1 No Data WORD n b1 b2 b 3 b 4 b 5 b 6 b7 b22 b23 b24 b25 b26 b 1 b 2 b3 WORD n-1 WORD n WORD n+1 Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 6 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Serializer Operation Mode (Continued) Serializer Operation: (Figure 6), DIRI = 1, No CKREF A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, this device enables the CKREF serialization mode. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered down and powered back up with a "logic 0" on CKREF. CKSI DP[1:24] STROBE DSO CKS0 No Data WORD n-1 No Data WORD n b 1 b 2 b3 b 4 b 5 b 6 b 7 b22 b23 b24 b25 b26 b1 b2 b3 WORD n-1 WORD n WORD n+1 Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 7 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this mode, the internal serializer circuitry is disabled; including the parallel data input buffers. If there is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 = 1), all deserializer output data pins are driven LOW until valid data is passed through the deserializer. Deserializer Operation: DIRI = 0 (Serializer Source: CKREF = STROBE) When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data. The word boundary is defined in the actual clock and data signal. Parallel data is generated at the time the word boundary is detected. The falling edge of CKP occurs approximately six bit times after the falling edge of CKSI. The rising edge of CKP goes high approximately 13 bit times after CKP goes LOW. The rising edge of CKP is generated approximately 13 bit times later. When no embedded word boundary occurs, no pulse is generated on CKP and CKP remains HIGH. WORD n WORD n+1 b19 b20 b24 b25 b26 b1 b2 WORD n-1 DSI b24 b25 b26 CKSI CKPO DP[1:24] WORD n-2 b1 b6 b7 b8 b9 WORD n-1 WORD n Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE) Deserializer Operation: DIRI = 0 (Serializer Source: CKREF does not = STROBE) The logical operation of the deserializer remains the same if the CKREF is equal in frequency to the STROBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer, however, differs because it has non-valid data bits sent between words. The duty cycle of CKP varies based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal is equal to the STROBE frequency. The falling edge of CKP will occurs six bit times after the data transition. The LOW time of the CKP signal is equal to half (13 bit times) of the CKREF period. The CKP HIGH time is equal to STROBE period - half of the CKREF period. Figure 8 is representative of a waveform that could be seen when CKREF is not equal to STROBE. If CKREF is significantly faster, additional non-valid data bits occur between data words. WORD n WORD n+1 bj+13 bj+14 b24 b25 b26 0 0 WORD n-1 DSI b24 b25 b26 CKSI CKPO DP[1:24] WORD n-2 0 0 bj bj+1 13 bit times 6 bit times WORD n-1 WORD n Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 8 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Embedded Word Clock Operation The FIN24AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a low clock pulse. This appears in the serial clock stream as 3 consecutive bit times where signal CKSO remains HIGH. To implement this sort of scheme, two extra data bits are required. During the word boundary phase, the data toggles either HIGH-then-LOW or LOW-then-HIGH dependent upon the last bit of the actual data word. Table 2 provides some examples of the actual data word and the data word with the word boundary bits added. Note that a 24-bit word is extended to 26-bits during serial transmission. Bit 25 and Bit 26 are defined with-respect-to Bit 24. Bit 25 is always the inverse of Bit 24, and Bit 26 is always the same as Bit 24. This ensures that a "0" "1" and a "1" "0" transition always occurs during the embedded word phase where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are stripped prior to the word being sent out the parallel port. resistor. If a FIN24AC device is configured as an unidirectional serializer, unused data I/O can be treated as unused inputs. If the FIN24AC is hardwired as a deserializer, unused data I/O can be treated as unused outputs. From Deserializer DP[n] To Serializer From Control Figure 9. LVCMOS I/O Differential I/O Circuitry The FIN24AC employs FSC proprietary CTL I/O technology. CTL is a low-power, low-EMI, differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the output buffer to which it is connected. This differs from LVDS, which uses a constant current source output, but a voltage sense receiver. Like LVDS, an input source termination resistor is required to properly terminate the transmission line. The FIN24AC device incorporates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor ensures proper termination regardless of direction of data flow. The relatively greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and a much lower voltage. During power-down mode, the differential inputs are disabled and powered down and the differential outputs are placed in a HIGH-Z state. CTL inputs have an inherent fail-safe capability that supports floating inputs. When the CKSI input pair of the serializer is unused, it can reliably be left floating. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected to VDD. When the CKSO output of the deserializer is unused, it should be allowed to float. LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDDP . The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source/sink current of 2mA at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH, the bi-directional LVCMOS I/Os are in a HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Unused LVCMOS input buffers must be tied off to either a valid logic LOW or a valid logic HIGH level to prevent static current draw due to a floating input. Unused LVCMOS output should be left floating. Unused bi-directional pins should be connected to GND through a high-value Table 2. Word Boundary Data Bits 24-Bit Data Words Hex 3FFFFFh 155555h xxxxxxh 24-Bit Data Word with Word Boundary Hex 1FFFFFFh 1155555h 1xxxxxxh Binary 0011 1111 1111 1111 1111 1111b 0101 0101 0101 0101 01010 0101b 0xxx xxxx xxxx xxxx xxxx xxxxb Binary 01 1111 1111 1111 1111 1111 1111b 01 0101 0101 0101 0101 0101 0101b 01 0xxx xxxx xxxx xxxx xxxx xxxxb (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 9 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer From Serializer From Control To Deserializer + - DS+ DS- + - Gated Termination (DS Pins Only) Figure 10. Bi-Directional Differential I/O Circuitry PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capable of transferring data at 26 times the incoming CKREF signal. The output of the PLL is a bit clock that is used to serialize the data. The bit clock is also sent source synchronously with the serial data stream. There are two ways to disable the PLL: by entering the Mode 0 state (S1 = S2 = 0) or by detecting a LOW on both the S1 and S2 signals. When any of the other modes are entered by asserting either S1 or S2 HIGH and by providing a CKREF signal. The PLL powers up and goes through a lock sequence. Wait the specified number of clock cycles prior to capturing valid data into the parallel port. When the SerDes chipset transitions from a power-down state (S1, S2 = 0, 0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer transitions LOW for a short duration, then returns HIGH. Following this, the signal level of the deserializer at CKP corresponds to the serializer signal levels. An alternate way of powering down the PLL is by stopping the CKREF signal either HIGH or LOW. Internal circuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references,however, are not disabled, allowing the PLL to power-up and re-lock in a lesser number of clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal, the PLL is reactivated. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 10 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Application Mode Diagrams Unidirectional Data Transfer BIT CK Gen. + - CKSO + - CKSI Work CK Gen Deserializer Control CKREF_M PLL CKP_S Serializer Control STROBE_M DP[1:12]_M Register DS Serializer + - + - Deserializer Register DP[1:12]_S Master Device Operating as a Serializer DIR = "1" S2 = S1 = "0" Slave Device Operating as a Deserializer DIR = "0" S2 = S1 = "0" Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode. In Master Operation, the device: 1. Is configured as a serializer at power-up based on the value of the DIRI signal. 2. Accepts CKREF_M word clock and generates a bit clock with embedded word boundary. This bit clock is sent to the slave device through the CKSO port. 3. Receives parallel data on the rising edge of STROBE_M. 4. Generates and transmits serialized data on the DS signals source synchronously with CKSO. 5. Generates an embedded word clock for each strobe signal. In Slave Operation, the device: 1. Is configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accepts an embedded word boundary bit clock on CKSI. 3. Deserializes the DS data stream using the CKSI input clock. 4. Writes parallel data onto the DP_S port and generates the CKP_S. CKP_S is only generated when a valid data word occurs. REFCK FIN24AC CKREF STROBE CNTL[0:1] FIN24AC CKSI DS CKP DP[23:24] DP[1:20] CNTL[0:1] DATA [0:19] CKSO DS Sending Unit DP[21:22] DP[1:20] DATA [0:19] Receiving Unit VDD DIRI S1 S2 DIRI S1 S2 Note: Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer. Figure 12. Unidirectional Serializer and Deserializer (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 11 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Base Unit FIN24AC CKREF CKSO DS CKSI CKSI DS STROBE DP[21:22] DP[1:20] FIN24AC CKP DP[23:24] DP[1:20] DP[21:22] STROBE CKREF Camera VSYNC/HSYNC LCD Unit LCD CKSO Camera Unit VSYNC/HSYNC DP[23:24] DIRO S1 S2 DIRI DIRO DIRI S1 S2 Disable GPIO PwrDwn Camera/LCD Select Figure 13. Multiple Units, Unidirectional Signals in Each Direction Figure 13 shows a half-duplex connectivity diagram. This connectivity allows for two unidirectional data streams to be sent across a single pair of SerDes devices. Data is sent on a frame-by-frame basis. For this mode, there must be some synchronization between when the camera sends its data frame and when the LCD sends its data. One option is to have the LCD send data during the camera blanking period. External logic may be needed for this mode of operation. Devices alternate frames of data controlled by a direction control and a direction sense. When DIRI on the righthand FIN24AC is HIGH, data is sent from the camera to the camera interface at the base. When DIRI on the right-hand FIN24AC goes LOW, is sent from the baseband process to the LCD. The direction is then changed at DIRO on the right-hand FIN24AC, indicating to the left-hand FIN24AC to change direction. Data is sent from the base LCD unit to the LCD. The DIRO pin on the left-hand FIN24AC is used to indicate to the base control unit that the signals are changing direction and the LCD is available to receive data. DIRI on the right-hand FIN24AC could typically use a timing reference signal, such as VSYNC from the camera interface, to indicate direction change. A derivative of this signal may be required to make sure that no data is lost in the final data transfer. Flex Circuit Design Guidelines The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB: Keep all four differential wires the same length. Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 12 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Supply Voltage ALL Input/Output Voltage Parameter Min. -0.5 -0.5 -65 Max. +4.6 +4.6 +150 +150 +260 Unit V V C C C kV kV LVDS Output Short-Circuit Duration TSTG TJ TL ESD Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 4 seconds) Human Body Model, 1.5k, 100pF All Pins CKSO, CKSI, DSO to GND Continuous >2 > 7.5 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VDDA, VDDS VDDP TA VDDA-PP Supply Voltage Supply Voltage Operating Temperature Supply Noise Voltage Parameter Min. 2.5 1.65 -30 Max. 2.9 3.6 +70 100 Unit V V C mVp-p (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 13 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer DC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol LVCMOS I/O VIH VIL VOH Parameter Input High Voltage Input Low Voltage Test Conditions Min. 0.65 x VDDP GND Typ.(2) Max. VDDP 0.35 x VDDP Unit V VDDP = 3.3 0.3 Output High Voltage IOH = -2.0 mA VDDP = 2.5 0.2 VDDP = 1.8 0.15 VDDP = 3.3 0.3 VOL IIN Output Low Voltage IOL = 2.0 mA VIN = 0V to 3.6V VDDP = 2.5 0.2 VDDP = 1.8 0.15 Input Current -5.0 5.0 A DIFFERENTIAL I/O IODH IODL IOZ IIZ VICM VGO RTRM RTRM Output High Source Current Output Low Sink Current Disabled Output Leakage Current Disabled Input Leakage Current VOS = 1.0V, Figure 14 VOS = 1.0V, Figure 14 CKSO, DSO = 0V to VDDS, S2 = S1 = 0V CKSI, DSI = 0V to VDDS, S2 = S1 = 0V -1.75 0.950 0.1 0.1 VGO + 0.80 0 80.0 80.0 100 100 120 120 5.0 5.0 mA mA A A V V 0.25 x VDDP V 0.75 x VDDP V Input Common Mode Range VDDS = 2.775 5% Input Voltage Ground Off-set Relative to Driver(3) CKSI Internal Receiver Termination Resistor DSI Internal Receiver, Termination Resistor See Figure 15 VID = 50mV, VIC = 925mV, DIRI = 0, | CKSI+ - CKSI- | = VID VID = 50mV, VIC = 925mV, DIRI = 0, | DSI+ - DSI- | = VID Notes: 2. Typical Values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified (except VOD and VOD). 3. VGO is the difference in device ground levels between the CTL driver and the CTL receiver. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 14 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Power Supply Currents Symbol IDDA1 IDDA2 IDDS1 IDDS2 IDD_PD Parameter VDDA Serializer Static Supply Current VDDA Deserializer Static Supply Current VDDS Serializer Static Supply Current VDDS Deserializer Static Supply Current Test Conditions All DP and Control Inputs at 0V or VDD , No CKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD , No CKREF, S2 = 0, S1 = 1, DIR = 0 All DP and Control Inputs at 0V or VDD , No CKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD , No CKREF, S2 = 0, S1 = 1, DIR = 0 Min. Typ. 450 550 4.0 4.5 0.1 9.0 14.0 9.5 17.0 11.0 15.5 5.5 6.0 4.0 5.5 7.5 10.0 8.0 8.5 10.0 12.0 Max. Units A A mA mA A VDD Power-Down Supply Current S1 = S2 = 0, All Inputs at GND or VDD IDD_PD = IDDA + IDDS + IDDP S2 = L S1 = H 2MHz 5MHz 5MHz 15MHz 10MHz 20MHz 2MHz 5MHz 5MHz 15MHz 10MHz 20MHz 2MHz 5MHz 10MHz 15MHz 26:1 Dynamic Serializer Power IDD_SER1 Supply Current IDD_SER1 = IDDA + IDDS + IDDP CKREF = STROBE S2 = H DIRI = H S1 = L See Figure 16 S2 = H S1 = H S2 = L S1 = H mA 1:26 Dynamic Deserializer Power CKREF = STROBE S2 = H IDD_DES1 Supply Current DIRI = L S1 = L IDD_DES1 = IDDA + IDDS + IDDP See Figure 16 S2 = H S1 = H 26:1 Dynamic Serializer Power IDD_SER2 Supply Current IDD_SER2 = IDDA + IDDS + IDDP NO CKREF STROBE Active CKSI = 15X Strobe DIRI = H, See Figure 16 mA mA AC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol tTCP Parameter CKREF Clock Period (2MHz-20MHz) Test Conditions See Figure 20 CKREF = STROBE S2 = 0 S2 = 1 S2 = 1 S2 = 0 S2 = 1 S2 = 1 S1 = 1 S1 = 0 S1 = 1 S1 = 1 S1 = 0 S1 = 1 Min. 200 66.0 50.0 1.1 x fST Typ.(4) T Max. 500 200 100 5.0 15.0 20.0 Units ns SERIALIZER INPUT OPERATING CONDITIONS fREF CKREF Frequency Relative to CKREF Strobe Frequency does not equal STROBE CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH/LOW See Figure 20 See Figure 20 MHz tCPWH tCPWL tCLKT tSPWH 0.2 0.2 0.5 0.5 90.0 T T ns ns (T x 4) / 26 (T x 22) / 26 (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 15 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Symbol fMAX Parameter Maximum Serial Data Rate Test Conditions CKREF x 26 S2 = 0 S2 = 1 S2 = 1 S1 = 1 S1 = 0 S1 = 1 Min. 52.0 130 260 2.5 2.0 1.1 x fSTROBE 33a + 1.5 -50.0 Typ.(4) Max. 130 390 520 Units Mb/s tSTC tHTC fREF DP(n) Setup to STROBE DP(n) Hold to STROBE DIRI = 1 See Figure 9 (f = 5MHz) ns ns 20.0 MHz CKREF Frequency Relative to CKREF Does Not Equal STROBE Strobe Frequency Transmitter Clock Input to Clock Output Delay See Figure 23, DIRI = 1, CKREF = STROBE SERIALIZER AC ELECTRICAL CHARACTERISTICS tTCCD tSPOS tTPLLS0 tTPLLD0 tTPLLD1 tS_DS tH_DS 35a + 6.5 250 200 30.0 20.0 1.4 -250 ns ps s s ns ns ps CKSO Position Relative to DS See Figure 26(5) Serializer PLL Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time Serial Port Setup Time, DS-to-CKSI Serial Port Hold Time, DS-to-CKS Deserializer Clock Output (CKP OUT) Period CKP OUT Low Time CKP OUT High Time Data Valid to CKP LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) See Figure 22 See Figure 27 See Figure 28(6) See Figure 25(7) See Figure 25(7) PLL AC ELECTRICAL CHARACTERISTICS DESERIALIZER INPUT OPERATION CONDITIONS DESERIALIZER AC ELECTRICAL CHARACTERISTICS tRCOP tRCOL tRCOH tPDV tROLH tROHL See Figure 21 See Figure 21 (Rising Edge Strobe) Serializer Source STROBE = CKREF where a = (1 /f ) / 26(8) See Figure 21 (Rising Edge Strobe) where a = (1 /f ) / 26(8) CL = 5pF, See Figure 18 50.0 13a-3 13a-3 8a-6 2.5 2.5 T 500 13a+3 13a+3 8a+1 ns ns ns ns ns ns Notes: 4. Typical Values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified (except VOD and VOD). 5. Skew is measured form either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid. 6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based on the operating mode of the device. 7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects. 8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of CKSO. Variation of the data with respect of the CKP signal is due to internal propagation delay differences of the data and CKP path and propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of CKP remains 13 bit times. (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 16 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Control Logic Timing Controls Symbol tPHL_DIR, tPLH_DIR Parameter Propagation Delay DIRI-to-DIRO Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW Min. Typ. Max. Units 17.0 25.0 25.0 25.0 2.0 25.0 65.0 ns ns ns ns s ns ns tPLZ, tPHZ Propagation Delay DIRI-to-DP tPZL, tPZH Propagation Delay DIRI-to-DP tPLZ, tPHZ Deserializer Disable Time: DIRI = 0, S0 or S1 to DP S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29 tPZL, tPZH Deserializer Enable Time: S0 or S1 to DP tPLZ, tPHZ Serializer Disable Time: S0 or S1 to CKSO, DS tPZL, tPZH Serializer Enable Time: S0 or S1 to CKSO, DS DIRI = 0,(9) S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29 DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28 DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH, Figure 28 Note: 9. Deserializer Enable Time includes the amount of time required for internal voltage and current references to stabilize. This time is significantly less than the PLL lock time and does not impact overall system startup time. Capacitance Symbol CIN CIO CIO-DIFF Parameter Capacitance of Input Only Signals, CKREF, STROBE, S1, S2, DIRI Test Conditions DIRI = 1, S1 = S2 = 0, VDD = 2.5V Min. Typ. 2.0 2.0 2.0 Max. Units pF pF pF Capacitance of Parallel Port Pins DP1:12 DIRI = 1, S1 = S2 = 0, VDD = 2.5V Capacitance of Differential I/O Signals DIRI = 0, S1 = S2 = 0, VDD = 2.775V (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 17 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms DS+ RL/2 Input RL/2 DSVOS VOD DUT + - DUT + - + - VGO 100 Termination Figure 14. Differential CTL Output DC Test Circuit Figure 15. CTL Input Common Mode Test Circuit T DP[1:12] CKREF CKS0CKS0+ DS+ DSb13 b14 b1 0 b2 1 b6 0 b7 1 b8 0 b11 0 b12 1 b1 1 b2 0 b6 1 b7 0 b8 1 b11 1 b12 0 b1 b2 666h 999h 666h Note: The "worst-case" test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency, unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.5V. Figure 16. "Worst-Case" Serializer Test Pattern tTLH 80% VDIFF 20% 80% tTHL 20% tROLH 80% DPn 20% 80% tROHL 20% VDIFF = (DS+) - (DS-) DS+ + - DPn 5pF 1000 5 pF DS- 100 Figure 17. CTL Output Load and Transition Times Figure 18. LVCMOS Output Load and Transition Times (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 18 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms (Continued) Setup Time STROBE DP[1:12] Data 10% 10% tTCP CKREF 50% VIH VIL tCPWH Setup: MODE0 = "0" or "1", MODE1 = "1", SER/DES = "1" tSTC tCLKT 90% 90% tCLKT Hold Time STROBE DP[1:12] Data tHTC 50% tCPWL Figure 19. Serial Setup and Hold Time Figure 20. LVCMOS Clock Parameters Data Valid CKP DP[1:12] Data tPDV tTPLS0 tRCOP VDD/VDDA 50% 25% tRCOL CKP 50% 75% tRCOH S1 or S2 CKREF CKS0 Setup: EN_DES = "1", CKSI, and DSI are valid signals. Note: CKREF signal is free running. Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters Figure 22. Serializer PLL Lock Time tTCCD STROBE CKS0CKS0+ Note: STROBE = CKREF VDD/2 VDIFF = 0 CKSICKSI+ CKP VDIFF = 0 tRCCD VDD/2 Figure 23. Serializer Clock Propagation Delay Figure 24. Deserializer Clock Propagation Delay (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 19 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms (Continued) CKSOtS_DS CKSICKSI+ DSI+ DSIVDIFF=0 VID/2 VDIFF=0 tH_DS CKSO+ DSO+ DSO- VDIFF = 0 VDIFF = 0 VID / 2 tSK(P-P) Note: Data is typically edge aligned with the clock. Figure 25. Differential Input Setup and Hold Times Figure 26. Differential Output Signal Skew tTPPLD0 CKREF tTPPLD1 S1 or S2 CKS0 CKS0 Note: CKREF Signal can be stopped either HIGH or LOW. Figure 27. PLL Loss of Clock Disable Time Figure 28. PLL Power-Down Time tPLZ(HZ) S1 or S2 tPZL(ZH) tPLZ(HZ) S1 or S2 tPZL(ZH) DS+,CKS0+ DS-,CKS0HIGH-Z DP Note: CKREF must be active and PLL must be stable. Note: If S1(2) transitioning, S2(1) must = 0 for test to be valid. Figure 29. Serializer Enable and Disable Time Figure 30. Deserializer Enable and Disable Times (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 20 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. BGA Embossed Tape Dimension T P0 D P2 E F K0 W Wc B0 Tc A0 P1 D1 User Direction of Feed Package 3.5 x 4.5 A0 D D1 E B0 0.1 0.1 0.05 Min. 0.1 TBD TBD 1.55 1.5 1.75 F 0.1 5.5 K0 P1 P0 P2 T TC W WC 0.1 Typ. Typ. 0/05 Typ. 0.005 0.3 Typ. 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3 lateral movement requirements (see sketches A, B, and C). 1.0mm maximum Note: 10. A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and 10 maximum B0 10 maximum component rotation Sketch A (Side or Front Sectional View) Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum Sketch C (Top View) Component Rotation Component lateral movement Component Rotation Shipping Reel Dimension W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/-0.2 13.0 13.0 13.0 Dia D Min. 20.2 20.2 20.2 Dim N Min. 178 178 178 Dim W1 +2.0/-0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 21 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Tape and Reel Specification (Continued) Dimensions are in millimeters unless otherwise noted. MLP Embossed Tape Dimension T P0 D P2 E F K0 W Wc B0 Tc A0 P1 D1 User Direction of Feed Package 5x5 6x6 A0 D D1 E B0 0.1 0.1 0.05 Min. 0.1 5.35 6.30 5.35 6.30 1.55 1.55 1.5 1.5 1.75 1.75 F 0.1 5.5 5.5 K0 P1 P0 P2 T TC W WC 0.1 Typ. Typ. 0/05 Typ. 0.005 0.3 Typ. 1.4 1.4 8 8 4 4 2.0 2.0 0.3 0.3 0.07 0.07 12 12 9.3 9.3 Note: 11. Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum B0 10 maximum component rotation Sketch A (Side or Front Sectional View) 1.0mm maximum Sketch C (Top View) Component Rotation Component lateral movement Component Rotation Shipping Reel Dimension W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/-0.2 13 13 13 Dia D Min. 20.2 20.2 20.2 Dim N Min. 178 178 178 Dim W1 +2.0/-0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 22 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Physical Dimensions Dimensions are in millimeters unless otherwise noted. 2X 0.10 C 3.50 2X 0.10 C (0.35) (0.6) 2.5 (0.5) (0.75) TERMINAL A1 CORNER INDEX AREA 4.50 0.5 3.0 0.5 O0.30.05 BOTTOM VIEW X42 0.15 0.05 CAB C (QA CONTROL VALUE) 0.890.082 0.450.05 0.210.04 1.00 MAX 0.10 C C SEATING PLANE 0.08 C 0.230.05 0.2+0.1 -0.0 LAND PATTERN RECOMMENDATION Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 23 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. (DATUM A) Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 24 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer (c) 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 www.fairchildsemi.com 25 |
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